1. Field of the Invention
The present invention relates to a stacked device comprising a stack of a master device and a plurality of slave devices, and to slave devices and master devices therefor.
2. Background Information
Stacked devices have been developed, which comprise a plurality of semiconductor devices for performing various processing tasks and a control device such as a CPU for controlling the semiconductor devices, which are stacked on a board. By stacking semiconductor devices on a board in this manner, it is possible to reduce the size and weight of the product containing the semiconductor devices. Here, each of the semiconductor devices is assigned, in advance, a specific ID (identifier), at the wafer fabrication stage. The control device can access each semiconductor devices based on this specific ID so as to control each of the semiconductor devices.
Furthermore, JP-2002-50735-A discloses a method for identifying semiconductor devices in a three-dimensional installation. FIG. 32 is a structural diagram of a three-dimensional stacked semiconductor device according to this JP-2002-50735-A. As shown in FIG. 32, on a first semiconductor device 1 are stacked a second and a third semiconductor device 2 and 3, having identical terminal structures. The back and the front sides of each semiconductor device are electrically connected by a through-wire that passes through the interior of the substrate. Furthermore, the terminals at the same positions on each of the semiconductor devices contact each other. By virtue of this structure, signals for controlling the devices can be transmitted in common from the control device to the first, second and third semiconductor devices 1, 2 and 3.
Each of the semiconductor devices is provided with a control terminal for inputting various control signals and a CS (chip select) terminal for inputting a select signal for putting the devices in the selected state. Control terminals for the first semiconductor device 1 include, for example, a control terminal 12a and a control terminal 12b. Furthermore, CS terminals for the first semiconductor device 1 include CS terminals 11a, 11b, 13a, 13b, 15a and 15b. The control terminal 12a on the back side 1a of the first semiconductor device 1 and the control terminal 12b, on the front side 1b thereof, are connected by a perpendicular through-wire 51. Here, the perpendicular through-wire is a through-wire that is perpendicular to the front and back sides, and which transmits various control signals. Furthermore, the control terminal 12b on the front side 1b of the first semiconductor device 1 contacts the control terminal 18a on the back side 2b of the second semiconductor device 2; and the control terminal 18b on the front side 2b of the second semiconductor device 2 contacts the control terminal 20a on the back side 3a of the third semiconductor device 3. By virtue of this structure, common control signals are sent to the first, second and third semiconductor devices 10, 20 and 30 by way of the perpendicular through-wires and the terminals, which contact each other.
Furthermore, the CS terminals 11a, 13a and 15a on the back side 1a of the first semiconductor device 1 are connected to the CS terminals 11b, 13b and 15b on the front side 1b thereof, by way of inclined through-wires 31, 33 and 35. Here, the inclined through-wires pass through the front and back sides of the semiconductor devices and intersect these front and back sides at an inclined angle. Furthermore, the CS terminal 11b on the front side 1b of the first semiconductor device 1 contacts the CS terminal 17a on the back side 2a of the second semiconductor device 2; and the CS terminal 13b on the front side 1b of the first semiconductor device 1 contacts the CS terminal 19a on the back side 2a of the second semiconductor device 2. The other CS terminals and the inclined through-wires are also interconnected as shown in FIG. 32. Here, a control device (not shown in the drawing) provided below the first semiconductor device 1 sends select signals for placing the semiconductor devices in the selected state by way of predetermined terminals, so as to access the desired semiconductor device.
For example, the select signal transmitted by way of the CS terminal 11a on the first semiconductor device 1 reaches the CS terminal 21b on the third semiconductor device 3 by way of: the CS terminal 11a→the through-wire 31→the CS terminal 11b→the CS terminal 17a→the through-wire 37→the CS terminal 17b→the CS terminal 21a→the through-wire 41→the CS terminal 21b. Consequently, the third semiconductor device 3 enters the selected state and the third semiconductor terminal 3 receives various control signals from the control device by way of the control terminals and the perpendicular through-wires. Likewise, the select signal transmitted by way of the CS terminal 13a on the first semiconductor device 1 reaches the CS terminal 19b on the second semiconductor device 2 by way of: the CS terminal 13a→the through-wire 33→the CS terminal 13b→the CS terminal 19a→the through-wire 39→the CS terminal 19b. Consequently, the second semiconductor device 2 enters the selected state. Furthermore, the select signal transmitted by way of the CS terminal 15a on the first semiconductor device 1 reaches the CS terminal 15b on the first semiconductor device 1 by way of: the CS terminal 15a→the through-wire 35→the CS terminal 15b. Consequently, the first semiconductor device 1 enters the selected state.
By selecting CS terminals so as to transmit select signals, it is possible to access each of the semiconductor devices separately.
However, if specific IDs are assigned beforehand at the wafer fabrication stage, it is necessary to store the predetermined IDs in the control device that controls the semiconductor devices beforehand. Accordingly, it is necessary to deal with the question of which semiconductors, having which IDs, are stacked in the device. In particular, it is extremely difficult to manage semiconductor devices according to individually assigned IDs, because a large number of semiconductor devices are fabricated in a single wafer.
In this regard, according to JP-2002-50735-A, it is not necessary to assign a specific ID to each semiconductor device when the wafer is fabricated, because each semiconductor device can be identified by the connections of the CS terminals and the inclined through-wires. However, in order to allow unique access to each of the semiconductor devices, via one CS terminal, it is necessary to stack the semiconductor devices with consideration given to the combinations of inclined through-wires and CS terminals. That is to say, in the aforementioned FIG. 32, only the third semiconductor device 3 can be accessed from the CS terminal 11a; only the second semiconductor device 2 can be accessed from the CS terminal 13a; and only the first semiconductor device 1 can be accessed from the CS terminal 15a. Accordingly, it is necessary to stack the semiconductor devices with consideration for the combinations of the CS terminals and the position of the semiconductor device to be accessed in the stack.
Furthermore, according to JP-2002-50735-A, in order to place specific semiconductor devices in selected states, it was, in particular, necessary to form inclined through-wires. Special operations are required to form inclined through-wires, and they can not easily be formed with high accuracy. Furthermore, it was necessary to provide perpendicular through-wires for connecting the control terminals with each other and inclined through-wires for connecting the CS terminals with each other, which is to say it was necessary to provide two types of through-wires, which complicated the manufacturing process.
Here, an object of the present invention is to provide technology allowing for the easy manufacture of a stacked device while identifying a plurality of devices that are stacked in the stacked device.
In view of the above, there exists a need for a slave device, master device, and stacked device which overcomes the above mentioned problems in the prior art. This invention addresses this need in the prior art as well as other needs, which will become apparent to those skilled in the art from this disclosure.